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Cryptographic algorithms on FPGA
Broda, Jan ; Jedlička, Petr (referee) ; Hajný, Jan (advisor)
The master thesis is focused on developing a demonstrator which is able to transmit data not only between operating system and network FPGA card with a UltraScale+ chip but also between two network FPGA cards. The theoretical part of the master thesis describes FPGA, developing on FPGA, programming languges that are used and develoment enviroment Vivado Design Suite. The demonstrator consists of two applications developed in C language which are used for communication between operating system and the network FPGA card and two components developed in VHDL langague which are used for communication throught a network module on the network FPGA card. The demonstrator allows inserting cryptographic algorithm which would work with transmitted data. For developing on the network FPGA card was used a Network Development Kit provided by a Liberouter team from CESNET association.
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Autonegotiation implementation for 25 - 100 Gbps Ethernet interfaces
Válek, Vladislav ; Jedlička, Petr (referee) ; Tomašov, Adrián (advisor)
This bachelor's thesis addresses the design of the auto-negotiation component for network interface cards controlled by FPGAs. Auto-negotiation function allows to advertise the available communication parameters, like the link speed, the transmission pause ability or Forward Error Correction (FEC) ability, by either side of the common link and determine the common abilities, which will be used to establish a connection. In the beginning, the internal parts of Xilinx UltraScale+ FPGA family are introduced with greater emphasis on the description of GTY transceivers. In the next chapter are introduced the mechanisms of auto-negotiation function as described in clause 73 of the IEEE 802.3-2018 standard. The design here is created for Ethernet interfaces running at speed 25~Gbps and is written in VHDL language. The next chapter describes the necessary steps which are required for the implementation on the FPGAs, where high-speed transceivers are in use. Function of the created design was then checked within a simulation and the correspondent results are also provided in this thesis. In the end, the testing of the designed auto-negotiation component took place for which the network card with Vitex 7 UltraScale+ FPGA was used. The testing process includes the use of the Integrated Logic Analyzer (ILA) which was inserted into final design. The achieved results from testing of both, the auto-negotiation process and surrounding physical layer processes, are described here with proper commentary.
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Applied use of DSP blocks in Intel FPGA
Kondys, Daniel ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This bachelor's thesis explores the utilization of DSP blocks located particularly on FPGA Stratix 10 DX 2800 for the implementation of a counter and a comparator. In the theoretical part, topics such as the protocol Ethernet, the FPGA technology and its relation with Network Interface Controllers are explained, followed by a~description of general design flow for digital circuits on FPGAs and a detailed insight on DSP blocks in the Virtex UltraScale+ XCVU7P and Stratix 10 DX 2800 FPGAs. The practical part focuses on the design, implementation and testing of the counter and comparator, followed by measurements of their impact on FPGA's resource utilization and maximum frequency. Lastly, it describes the integration of these components into modules that are part of the COMBO-400g1 Network Interface Connector firmware and analyzes their impact on FPGA's resource utilization and maximum frequency.
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High-Speed Packet Data DMA Transfers to FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Martínek, Tomáš (advisor)
This thesis deals on the design, implementation, testing and measuring of a firmware module for FPGA chips, which enables DMA transfers of network data from computer RAM to the FPGA chip placed on a network interface card. These transfers are carried out using a PCIe bus on the speed of up to 100 Gbps with the possible support of speeds 200 Gbps and 400 Gbps. The goal of this technology is to allow network data processing for the purpose of maintenance of backbone network nodes and data centers. The module is designed so it can be used on different types of FPGA chips, mainly those produced by companies Xilinx and Intel.
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Cryptographic algorithms on FPGA
Broda, Jan ; Jedlička, Petr (referee) ; Hajný, Jan (advisor)
The master thesis is focused on developing a demonstrator which is able to transmit data not only between operating system and network FPGA card with a UltraScale+ chip but also between two network FPGA cards. The theoretical part of the master thesis describes FPGA, developing on FPGA, programming languges that are used and develoment enviroment Vivado Design Suite. The demonstrator consists of two applications developed in C language which are used for communication between operating system and the network FPGA card and two components developed in VHDL langague which are used for communication throught a network module on the network FPGA card. The demonstrator allows inserting cryptographic algorithm which would work with transmitted data. For developing on the network FPGA card was used a Network Development Kit provided by a Liberouter team from CESNET association.
|
|
|
Autonegotiation implementation for 25 - 100 Gbps Ethernet interfaces
Válek, Vladislav ; Jedlička, Petr (referee) ; Tomašov, Adrián (advisor)
This bachelor's thesis addresses the design of the auto-negotiation component for network interface cards controlled by FPGAs. Auto-negotiation function allows to advertise the available communication parameters, like the link speed, the transmission pause ability or Forward Error Correction (FEC) ability, by either side of the common link and determine the common abilities, which will be used to establish a connection. In the beginning, the internal parts of Xilinx UltraScale+ FPGA family are introduced with greater emphasis on the description of GTY transceivers. In the next chapter are introduced the mechanisms of auto-negotiation function as described in clause 73 of the IEEE 802.3-2018 standard. The design here is created for Ethernet interfaces running at speed 25~Gbps and is written in VHDL language. The next chapter describes the necessary steps which are required for the implementation on the FPGAs, where high-speed transceivers are in use. Function of the created design was then checked within a simulation and the correspondent results are also provided in this thesis. In the end, the testing of the designed auto-negotiation component took place for which the network card with Vitex 7 UltraScale+ FPGA was used. The testing process includes the use of the Integrated Logic Analyzer (ILA) which was inserted into final design. The achieved results from testing of both, the auto-negotiation process and surrounding physical layer processes, are described here with proper commentary.
|
|
|
High-Speed Packet Data DMA Transfers to FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Martínek, Tomáš (advisor)
This thesis deals on the design, implementation, testing and measuring of a firmware module for FPGA chips, which enables DMA transfers of network data from computer RAM to the FPGA chip placed on a network interface card. These transfers are carried out using a PCIe bus on the speed of up to 100 Gbps with the possible support of speeds 200 Gbps and 400 Gbps. The goal of this technology is to allow network data processing for the purpose of maintenance of backbone network nodes and data centers. The module is designed so it can be used on different types of FPGA chips, mainly those produced by companies Xilinx and Intel.
|
|
|
Applied use of DSP blocks in Intel FPGA
Kondys, Daniel ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This bachelor's thesis explores the utilization of DSP blocks located particularly on FPGA Stratix 10 DX 2800 for the implementation of a counter and a comparator. In the theoretical part, topics such as the protocol Ethernet, the FPGA technology and its relation with Network Interface Controllers are explained, followed by a~description of general design flow for digital circuits on FPGAs and a detailed insight on DSP blocks in the Virtex UltraScale+ XCVU7P and Stratix 10 DX 2800 FPGAs. The practical part focuses on the design, implementation and testing of the counter and comparator, followed by measurements of their impact on FPGA's resource utilization and maximum frequency. Lastly, it describes the integration of these components into modules that are part of the COMBO-400g1 Network Interface Connector firmware and analyzes their impact on FPGA's resource utilization and maximum frequency.
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